Ldrd arm instruction svc

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ARM and Thumb instruction summary gives an overview of the instructions available in the ARM and Thumb LDRD, Load Registers with two words, Memory access instructions, 5E, x6M SVC (formerly SWI ), SuperVisor Call, SVC, All.
Avoid using same register for <Rn> and <Rxf> when using LDRD because of an The TBB instruction uses a branch table of byte size offset, and TBH uses a
svc. Supervisor call (previously swi). 16-bit Thumb [ARMv4T, ARMv5T*, ARMv6*, ARMv7]. SVC, #<imm8>. ARM [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
5-117. 5.18. Determining the instruction set state from an SVC handler . Uses load (LDRD) and store (STRD) instructions that act on two words of data.

The purpose of this manual is to describe the ARM instruction set architecture, including of the enhanced DSP variant of the ARM architecture omitted the LDRD, where <mode> is the appropriate one of usr, svc (for Supervisor mode), abt,
Your access to the information in this ARM Architecture Reference Manual is conditional SVC instruction, generating a Supervisor Call (SVCall) exception that the If A1 and A2 are two word loads generated by an LDRD instruction or two
Entered on reset or when a Supervisor Call instruction (SVC) (for example LDRD and STRD doubleword memory transfers), or to align with cache boundaries.Instruction, Offset range, Architectures. ARM LDR , LDRB, +/– 4095, All. ARM LDRSB , LDRH , LDRSH, +/– 255, All. ARM LDRD, +/– 255, 5E. Thumb, 32-bit LDR

QUESTION: The Cortex-M cores support the SuperVisor Call (SVC) instruction, with that the user can trigger an exception. This can become handy, if e. g. the

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